Front End Design Verification Engineer

Who You Are

• A hands-on verification engineer who enjoys digging into complex processor behavior and finding subtle bugs.
• Comfortable working with CPU front-end concepts such as instruction fetch, branch prediction, instruction decode, queues, and dispatch.
• A strong problem solver who can move between specifications, RTL, simulations, and waveforms to identify root causes.
• Collaborative and proactive, with the ability to work closely with architects, RTL designers, and other DV engineers.
• Curious about high-performance CPUs and excited to learn how microarchitectural decisions impact real-world processor performance.

What We Need

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
• Solid understanding of CPU architecture, with familiarity in areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.
• Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools.
• Strong programming skills in C/C++ and/or Python, with the ability to collaborate effectively across architecture, RTL, DV, and software teams.

What You Will Learn

• Gain deep experience verifying the front end of a high-performance, out-of-order RISC-V CPU.
• Learn how instruction fetch, branch prediction, decode, and dispatch work together to keep a modern CPU pipeline running efficiently.
• Develop expertise in verifying speculative execution and the complex corner cases created by branches, redirects, exceptions, and pipeline flushes.
• Learn how architectural specifications and microarchitectural designs translate into RTL and comprehensive verification environments.
• Work alongside CPU architects and RTL engineers on processors designed for demanding AI, HPC, and high-performance computing workloads.