Physical Design CPU Methodology Engineer

Who you are

• You are an experienced Physical Design Engineer with 10+ years of ASIC/SoC/CPU experience, ideally focused on high-performance CPUs or similarly complex digital designs.
• You bring deep expertise across RTL-to-GDS implementation and signoff, including timing closure, power optimization, SI, EM/IR, extraction, and physical verification.
• You have built or owned physical design methodology, automation, or CAD flows and are highly skilled in Tcl, Python, Perl, or similar scripting languages.
• You are a technical leader who can influence across teams, mentor engineers, and drive standards across geographically distributed organizations.

What we need

• Define and own scalable CPU physical design methodology spanning synthesis, floorplanning, power planning, place and route, CTS, extraction, STA, SI, EM/IR, and physical verification.
• Explore AI/ML-enabled PD tooling, begin synthesis and PnR of CPU partitions, and start developing the new program RM flow.
• Drive automation, constraints, quality metrics, signoff criteria, dashboards, checkers, and debug workflows that improve predictability, turnaround time, and PPA.
• Partner with architecture, RTL, circuit, DFT, CAD, program, data, and EDA vendor teams to enable advanced nodes and productize AI/ML across physical design.

What you will learn

• How to apply AI/ML to physical design for hotspot prediction, congestion forecasting, timing-risk classification, ECO prioritization, IR-drop screening, and flow tuning.
• How to build reliable, explainable, production-ready data infrastructure, including feature collection, validation, and signoff integration.
• How to evaluate AI-enabled EDA capabilities and determine where data-driven optimization delivers measurable value over conventional heuristics.
• How to scale CPU methodology, automation, and AI/ML deployment across advanced-node programs, foundries, teams, and the broader organization.