Principal Digital Design Engineer
San Jose, United States
- Posted 3w ago
- From Astera Labs’s careers page
- Location
- San Jose, United States
- Level
- Principal
- Experience
- 8+ years
- Department
- Engineering
Opens the listing on job-boards.greenhouse.io
Let the right jobs find you
In your inbox every Wednesday and SaturdayPersonalised suggestions from verified career pages, matched to your role, location, level and skills.
About the role
Principal Digital Design Engineer:
Overview
Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.
Key Responsibilities
- Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
- Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
- Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
- Work closely with post-silicon teams to facilitate silicon bring-up and debug.
- Mentor junior engineers to develop their technical skills and expertise.
- Actively contribute to the development and improvement of silicon development processes.
- Drive designs to production, ensuring accountability for quality, schedule, and overall design success.
Required Qualifications:
Education & Experience:
- Bachelor’s degree in electrical engineering or equivalent.
- 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets
Digital Design Expertise:
- Architecture definition and micro-architecture development
- RTL coding, functional simulation, and synthesis
- Timing closure and gate-level simulation (GLS)
- Design for test (DFT) implementation
- Production experience with advanced CMOS nodes (≤7nm)
Protocols & Integration:
- Deep expertise in at least one high-speed protocol—PCIe, Ethernet, InfiniBand, DDR, or similar
- Third-party IP integration and verification.
- Block-level design ownership from architecture through GDS
Tools & Methodologies:
- Proficiency with Cadence and/or Synopsys digital design flows
- Familiarity with UVM-based verification methodologies.
- Silicon bring-up, debug, and failure analysis expertise
Professional Attributes:
- Strong work ethic with the ability to balance multiple priorities in a dynamic environment
- Excellent communication and collaboration skills; comfortable working cross-functionally with global teams
- Self-directed learner who thrives with minimal supervision and adapts quickly to changing requirements
- Customer-focused mindset with ability to translate business needs into technical excellence
Preferred Qualifications
- Track record of delivering multiple high-performance designs to production in data-center environments
- Hands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints
- Familiarity with standard embedded processor subsystems (RISC-V, Arm, etc.)
- Proven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality
Skills they ask for
Pick one to see other roles that ask for it.
- Micro architecture definition
- Data architecture development
- Rtl coding
- Functional simulation
- Rtl synthesis
- Timing closure
- Gate level simulation gls
- Design for test dft implementation
- Production experience with advanced cmos nodes 7nm
- Pc ie
- Ethernet
- Infini band
- Ddr
- Third party ip integration and verification
- Cadence
About Astera Labs
Connectivity solutions for rack-scale AIAstera Labs develops semiconductor connectivity solutions for rack-scale AI systems, including PCIe, CXL, Ethernet, and other interconnect technologies.
See all 50 roles at Astera LabsMore roles at Astera Labs
See all 50- Principal Ecosystem Partner ManagerSan Jose · Principal · On-siteBusiness Development · Principal · On-siteSan Jose, United States2d
- Principal Product Applications EngineerSan Jose · PrincipalEngineering · PrincipalSan Jose, United States2d
- PLM Change AnalystSan JoseQuality AssuranceSan Jose, United States3d
- Principal Hardware NPI Program ManagerSan Jose · PrincipalProject and Program Management · PrincipalSan Jose, United States4d
Let the right jobs find you
In your inbox every Wednesday and SaturdayPersonalised suggestions from verified career pages, matched to your role, location, level and skills.