Lead Logic Design for UALink IP/Subsystem Engineer

Job Summary

Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.

Key Responsibilities

• Lead UALink IP/subsystem RTL development.
• Translate protocol requirements into detailed microarchitecture.
• Design high-performance control and data-path logic.
• Work on buffering, arbitration, flow control, ordering, and error handling.
• Develop and review SystemVerilog RTL.
• Drive performance, area, power, and latency optimization.
• Collaborate with verification, SoC integration, and physical design teams.
• Debug complex functional and integration issues.
• Review RTL and mentor engineers.
• Support silicon debug and issue resolution.

Required Skills

• Strong RTL and microarchitecture experience.
• Experience with high-speed interconnects.
• Strong understanding of data movement, flow control, arbitration, and buffering.
• Excellent SystemVerilog/Verilog skills.
• Experience with CDC, lint, synthesis, and timing.
• Strong debugging and technical leadership skills.

Preferred

• Direct UALink experience.
• Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.
• Experience with AI/accelerator or high-performance compute SoCs.