Principal Advanced Packaging Engineer
San Jose, United States
- Posted 3w ago
- From Astera Labs’s careers page
- Location
- San Jose, United States
- Level
- Principal
- Experience
- 8+ years
- Department
- Engineering
Opens the listing on job-boards.greenhouse.io
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About the role
About the Role
Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips. This is a senior individual contributor role focused on setting technical direction and driving packaging technology development for NPO and CPO products.
Responsibilities
- Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
- Define and optimize wafer-level, panel-level, or die-level packaging process flows.
- Drive EIC-to-PIC integration and broader optical device integration efforts.
- Select and qualify packaging materials for advanced packaging.
- Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.
- Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.
- Develop and maintain packaging PDKs and design rules for NPO and CPO products.
Basic Qualifications:
- B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
- 8+ years of experience in semiconductor or advanced packaging engineering, with demonstrated technical leadership.
- Deep expertise in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and overmold across wafer-, panel-, and die-level flows.
- Experience with silicon photonics chip packaging and EIC/PIC integration.
- Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.
- Proven track record of equipment and process qualification with OSAT or tool suppliers.
- Experience with PDK development and packaging design rule authoring.
- Strong foundation in yield analysis, reliability characterization, and process capability methodologies such as Cpk and SPC.
Preferred Qualifications:
- Hands-on experience with CPO or NPO product development.
- Experience with optical coupling or waveguide alignment for photonic integration.
- Familiarity with DFM and DFT for advanced packaging.
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About Astera Labs
Connectivity solutions for rack-scale AIAstera Labs develops semiconductor connectivity solutions for rack-scale AI systems, including PCIe, CXL, Ethernet, and other interconnect technologies.
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