Senior Packaging Integration Lead
San Jose, United States
- Posted 2w ago
- From Astera Labs’s careers page
- Location
- San Jose, United States
- Level
- Senior
- Experience
- 5+ years
- Department
- Other
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About the role
Job Description
We are seeking a Senior Packaging Integration Lead to serve as the single-threaded packaging owner for one or more of Astera Labs’ advanced connectivity products. This role owns the end-to-end packaging solution from customer requirements and package architecture definition through development, qualification, and production ramp and represents packaging across the customer, internal cross-functional teams, business units, and the OSAT, foundry, and substrate supply base.
This is a senior individual-contributor technical leadership role who can set packaging technical direction, make architecture and technology-selection decisions, and drive alignment across stakeholders without direct authority. You will partner with packaging leadership on strategy while owning the technical direction for your products — defining package architecture and test vehicles to de-risk technology, and guiding execution engineers and external partners to deliver robust, manufacturable packages on schedule.
Key Responsibilities
- Own the packaging solution end-to-end for assigned products — serve as the single point of accountability from a packaging standpoint across definition, development, qualification, and production ramp
- Act as the primary packaging interface to the customer: capture and translate customer packaging, mechanical, thermal, SIPI, and reliability requirements into package architecture, specifications, and a clear execution roadmap
- Define package architecture, structure and technology selection (e.g., 2.5D/3D integration, chiplet/interposer, CoWoS-class, organic substrate) with feasibility, cost, performance, and manufacturability trade-off analysis
- Define and drive test vehicle (TV) strategy and requirements to de-risk new package technology, characterize interconnect/SIPI performance, and validate assembly and reliability ahead of product builds
- Represent packaging across internal cross-functional teams — silicon design, package design, SIPI, thermal, product engineering, test engineering, validation, quality, and operations — and align packaging requirements to product and business-unit roadmaps
- Partner with product planning, architecture, and program management on product roadmap, packaging feasibility, technology readiness, cost targets, and schedule commitments
- Set technical direction with OSAT, foundry, and substrate partners — driving technology selection, design-rule alignment, and development roadmaps across the supply base
- Own package definition deliverables and sign-offs, including POR/TOR, design rules, stack-up, package BOM, DFM alignment, and pre-tape-out design-integration readiness
- Drive risk identification, technology-gap closure, and mitigation across the product’s packaging roadmap; escalate and resolve critical cross-functional and supplier issues with urgency.
- Communicate packaging status, risks, and key decisions to executive leadership, customers, and cross-functional stakeholders and external partners.
Basic Qualifications
- B.S. or M.S. in Materials Science, Electrical Engineering, Mechanical Engineering, Chemical Engineering, or a related discipline; advanced degree preferred.
- 5-7+ yrs of experience in advanced packaging technologies such as 2.5D/3D integration, TSV, chiplets, and interposers. Optical / co-packaged optics experience is a plus.
- Demonstrated end-to-end ownership of a product or platform packaging solution, from definition and architecture through qualification and production ramp
- Experience defining package architecture and driving technology selection, including trade-off analysis across performance, cost, reliability, and manufacturability
- Experience defining test vehicles and characterization/qualification strategies to de-risk new packaging technology.
- Direct customer-facing experience translating product and system requirements into package specifications and commitments.
- Strong architecture-level understanding of signal/power integrity (SIPI), thermal, and thermo-mechanical reliability considerations in advanced packages
- Proven ability to lead and influence across internal cross-functional teams, business units, and external OSAT/foundry/substrate partners without direct authority.
- Hands-on background working with foundries, OSATs, substrate suppliers, and material vendors.
- Excellent communication, organizational, and executive-level presentation skills, with the ability to drive alignment across globally distributed teams.
Preferred Qualifications
- Experience with UCIe / die-to-die interconnect and high-bandwidth chiplet integration
- Experience with CoWoS-class, silicon-bridge, or advanced fan-out packaging platforms
- Experience with co-packaged optics / optical packaging for scale-up connectivity
- Track record engaging foundry and OSAT partners on advanced-packaging technology roadmaps
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About Astera Labs
Connectivity solutions for rack-scale AIAstera Labs develops semiconductor connectivity solutions for rack-scale AI systems, including PCIe, CXL, Ethernet, and other interconnect technologies.
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