Physical Design Engineer, Timing

Who You Are

• A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation.
• Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff.
• Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners.
• A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams.

What We Need

• Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results.
• Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and keep execution progressing through tapeout.
• Develop and validate bottom-up constraints while partnering with Design and DFT teams on methodology updates and closure requirements.
• Use Python, Perl, and Tcl for automation and flow development; experience with SPICE, PNR, placement, CTS, routing, post-route optimization, DFT, or AI-based automation is a plus.

What You Will Learn

• How to develop scalable timing models, constraints, and closure strategies across multiple levels of design hierarchy.
• How clocking, guardbanding, derates, uncertainties, CDC, RDC, and process corners influence timing convergence.
• How timing, physical design, Design, and DFT methodologies come together to deliver successful tapeouts.
• How to improve implementation and signoff workflows through scripting, automation, flow development, and emerging AI-enabled solutions.