Sr. Engineer, Performance Infrastructure (RISC-V)

Who You Are

• Great at identifying problems and developing solutions, with a bias toward owning the systems you build.
• Enjoys building tools and optimizing workflows so other engineers can move faster.
• Strong Linux systems engineer, comfortable wrangling lab machines, clusters and flaky hardware platforms.
• Skilled in Python and shell scripting, with solid CI (GitLab) and container experience.
• Experienced automating at scale — job scheduling, artifact management, databases and dashboarding; curiosity about CPU performance is a plus, deep microarchitecture background is not required.

What We Need

• Build and maintain benchmarking automation and CI pipelines that run SPEC and real-world workloads across RISC-V silicon, FPGA/emulation platforms and performance models.
• Own SimPoint generation and management infrastructure.
• Build performance-data collection into databases, with dashboards and visualization tools on top, so trends and regressions are visible without manual effort.
• Develop workload capture and replay tooling (QEMU- and CRIU-based checkpointing) so perf engineers can trace and analyze workloads reproducibly.
• Collaborate closely with performance and software engineers on both teams to understand their flows and remove the infrastructure friction from them.

What You Will Learn

• End-to-end exposure to CPU performance work, from workload capture through analysis and convergence.
• Hands-on experience with pre-silicon and post-silicon performance platforms — models, emulation, FPGA and real RISC-V hardware.
• Integration of open-source and industry-standard tools into production-grade flows.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU and AI challenges.