Post-Silicon Lab Manager

Who You Are

• You hold a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a similar technical field, and you have 8–12+ years in semiconductor hardware, including 3+ years leading a post-silicon validation, characterization, or hardware lab team focused on CPUs.
• You know high-speed interfaces (PCIe, DDR/GDDR/HBM, SerDes) and fabric links in depth, and you're hands-on with board-level debug tools.
• You bring a startup mindset. You stay calm and quick when troubleshooting physical hardware under tight tape-out and silicon-arrival deadlines.
• You communicate clearly across functions and keep remote, multi-site teams aligned from the Santa Clara hub.

What We Need

• Run day-to-day lab operations for CPU post-silicon validation, power/performance assessment, and debug, with lab infrastructure aligned to tape-out and bring-up schedules.
• Lead the lab environment for first-silicon power-on, system bring-up, and platform validation, including board-level fixes to salvage eval boards or meet new validation needs.
• Deploy and maintain server racks, data acquisition, power telemetry rigs, and automated test benches for multi-core CPU and chiplet-based systems. Manage the CapEx budget for scopes, logic/protocol analyzers, and traffic generators.
• Own inventory, calibration cycles, silicon allocation tracking, and lab safety compliance using JIRA, Confluence, and lab scheduling tools.

What You Will Learn

• How to bring up first silicon on advanced multi-core CPU and chiplet architectures, from power-on to full platform validation.
• How to build and scale a world-class post-silicon lab at a fast-moving company.
• How to debug critical post-silicon issues alongside the Emulation, Silicon Design, Software, and Architecture teams.
• How your lab's capacity planning and infrastructure decisions shape silicon schedules and product success.