Senior CPU Design Verification Engineer

Role Summary:

We are seeking a Senior CPU Design Verification Engineer to own block- and subsystem-level DV for advanced out-of-order (OoO) CPU cores. You will work closely with micro-architects and RTL designers to verify complex front-end designs including branch prediction, instruction decodes, execution pipelines, memory systems, and coherence protocols using modern, coverage-driven methodologies.

Key Responsibilities:

Verification Planning & Ownership

• Drive verification for key OoO CPU blocks, including front-end fetch, branch prediction, and decode; rename and register mapping; issue queues, schedulers, and execution units; reorder buffer (ROB), retirement, exceptions, and flush/replay; load-store unit (LSU), store buffer, atomics/LR-SC, and fences; and L1 caches, TLBs, MMU interfaces, and coherence interfaces.
• Derive verification plans from architecture and micro-architecture specs, with emphasis on speculative execution flows and pipeline hazards, memory ordering and consistency model compliance, and interaction with the cache hierarchy and coherence.

Testbench & Environment Development

• Develop and maintain SystemVerilog/UVM testbenches, including UVM agents, monitors, scoreboards, and reference models.
• Build constrained-random stimulus and directed tests for OoO corner cases.
• Implement self-checking mechanisms for instruction retirement and architectural state, LSU/memory ordering, atomics and fence behavior, and TLB, page-table, and privilege/protection flows.

Coverage & Quality

• Define and track functional, code, and assertion coverage; identify gaps and add tests or monitors to close them.
• Create and maintain SVA assertions for key micro-architectural properties, including no deadlock or livelock in scheduler, ROB, and LSQ; correct handling of mispredicts, exceptions, interrupts, and flush paths; and correct data forwarding and hazard resolution.
• Analyze regression results, triage failures, and drive issues to closure with design and architecture teams.

Debug & Collaboration

• Debug complex failures in speculation and replay, load-store ordering and memory consistency violations, and TLB/MMU corner cases and privilege/protection issues.
• Collaborate with micro-architecture and RTL teams on fixes and design clarifications, performance and modeling teams to align micro-architectural behavior and verification scenarios, and post-silicon and validation teams to correlate pre- and post-silicon issues.

Methodology & Mentoring

• Contribute to DV methodology improvements, including UVM components, coverage strategies, and regression flows.
• Provide guidance and code reviews to junior engineers on testbench design, stimulus generation, and debug.

Required Qualifications:

• Education: BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience: Typically 5-10 years of ASIC/SoC/IP design verification experience. Direct experience verifying out-of-order or superscalar CPU cores (or closely related high-performance pipelines).
• Technical skills: Strong proficiency in SystemVerilog and UVM (or equivalent class-based DV methodology). Solid understanding of CPU micro-architecture, including fetch/decode, rename, ROB, issue/execute, bypassing, commit; LSU, store buffer, atomics/LR-SC, fences, and memory ordering; and L1 caches, TLBs, page-table walkers, and basic coherence concepts. Hands-on experience with constrained-random and coverage-driven verification, writing and debugging SVA assertions, and industry-standard simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
• Soft skills: Strong problem-solving and debug skills on complex, corner-case bugs. Effective communication and teamwork across DV, design, and architecture. Ability to work independently on complex blocks while contributing to a larger project.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in India. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.