Senior Design Verification Engineer

Role Summary:

We are seeking a Senior Design Verification Engineer to own block- and subsystem-level DV for advanced out-of-order (OoO) CPU cores. You will work closely with micro-architects and RTL designers to verify complex execution pipelines, memory systems, and coherence protocols using modern, coverage-driven methodologies.

Key Responsibilities:

• Drive verification for key OoO CPU blocks, including front-end fetch, branch prediction, and decode; rename and register mapping; issue queues, schedulers, and execution units; reorder buffer (ROB), retirement, exceptions, and flush/replay; load-store unit (LSU), store buffer, atomics/LR-SC, and fences; L1 caches, TLBs, MMU interfaces, and coherence interfaces.
• Derive verification plans from architecture and micro-architecture specs, with emphasis on speculative execution flows, pipeline hazards, memory ordering and consistency compliance, and cache hierarchy and coherence interaction.
• Develop and maintain SystemVerilog/UVM testbenches, including UVM agents, monitors, scoreboards, and reference models.
• Create constrained-random stimulus and directed tests for OoO corner cases.
• Implement self-checking mechanisms for instruction retirement, architectural state, LSU and memory ordering, atomics, fence behavior, and TLB, page-table, and privilege/protection flows.
• Define and track functional, code, and assertion coverage; identify gaps and add tests or monitors to close them.
• Create and maintain SVA assertions for key micro-architectural properties, such as no deadlock or livelock in scheduler, ROB, and LSQ, correct handling of mispredicts, exceptions, interrupts, and flush paths, and correct data forwarding and hazard resolution.
• Analyze regression results, triage failures, and drive issues to closure with design and architecture teams.
• Debug complex failures in speculation and replay, load-store ordering, memory consistency violations, and TLB/MMU corner cases.
• Collaborate with micro-architecture and RTL teams on fixes and design clarifications, performance and modeling teams on aligned verification scenarios, and post-silicon validation teams to correlate pre- and post-silicon issues.
• Contribute to DV methodology improvements, including UVM components, coverage strategies, and regression flows.
• Provide guidance and code reviews to junior engineers on testbench design, stimulus generation, and debug.

Required Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Typically 5-10 years of ASIC/SoC/IP design verification experience.
• Direct experience verifying out-of-order or superscalar CPU cores (or closely related high-performance pipelines).
• Strong proficiency in SystemVerilog and UVM (or equivalent class-based DV methodology).
• Solid understanding of CPU micro-architecture, including fetch/decode, rename, ROB, issue/execute, bypassing, commit, LSU, store buffer, atomics/LR-SC, fences, memory ordering, L1 caches, TLBs, page-table walkers, and basic coherence concepts.
• Hands-on experience with constrained-random and coverage-driven verification, writing and debugging SVA assertions, and industry-standard simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
• Strong problem-solving and debug skills on complex, corner-case bugs.
• Effective communication and teamwork across DV, design, and architecture.
• Ability to work independently on complex blocks while contributing to a larger project.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in India. Any offer of employment is also contingent on the Company verifying that you are authorized for access to export-controlled technology under applicable export control laws or, if not already authorized, on our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.