Senior Engineer - Design Verification

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive's compute platforms enable leading technology companies to innovate and deliver advanced solutions across chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer markets.

About the Role

SiFive is looking for a Senior Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem used in high-performance SoCs.

This is a T3 / Senior Engineer individual-contributor role within the Interconnect horizontal area, focused on coherent interconnect and related subsystem behavior.

In this role, you will work across architecture, RTL, formal, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, quality-of-service behavior, and subsystem integration across multiple interface types and bridge paths.

Responsibilities

• Understand the coherent interconnect architecture and create effective verification strategies and test plans for the assigned area.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, and error handling.
• Verify subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including conversion, buffering, deinterleaving, and related data-movement behavior.
• Define and execute directed and constrained-random tests that expose corner cases in coherency, concurrency, ordering, credits, arbitration, QoS behavior, and integration scenarios.
• Analyze failures, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Collaborate closely with architecture, design, formal, and software teams to clarify requirements, review specifications, and improve verification quality early in the development cycle.
• Write functional coverage, analyze coverage results, and close coverage holes to ensure verification completeness and signoff quality.
• Contribute reusable methodology, automation, and debug improvements that raise team-wide productivity and verification quality.

Minimum Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of relevant experience in IP, subsystem, or SoC functional verification, preferably in coherent interconnect, cache, memory-system, or CPU-subsystem verification.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Solid understanding of cache-coherent systems, on-chip interconnects, memory-subsystem behavior, and verification of ordering and flow-control semantics.
• Experience creating test plans, building testbenches, writing assertions, analyzing coverage, and debugging complex design issues.
• Experience verifying protocol behavior such as ordering, backpressure, buffering, arbitration, flow control, and error handling.
• Strong debugging skills and the ability to root-cause issues across specification, RTL, and verification environment layers.
• Strong problem-solving skills and the ability to work effectively across architecture, design, and verification teams.

Preferred Qualifications

• Direct experience verifying coherent interconnect, NoC, cache, or memory-subsystem functionality in multicore or high-performance SoCs.
• Experience with subsystem integration and protocol interactions across multiple interfaces or bridge paths.
• Familiarity with one or more industry protocols such as AXI, CHI, ACE, CXL, UCIe, or similar high-performance interface standards.
• Familiarity with scripting and automation using Python or similar languages.
• Experience with formal verification, performance-oriented verification, or emulation / FPGA-assisted debug.
• Experience contributing reusable infrastructure or methodology improvements that benefit a broader DV team.

What Success Looks Like

• Verification plans are complete and aligned with the highest architectural and protocol risks.
• Critical coherent-interconnect bugs are found early, debugged efficiently, and closed with durable fixes.
• Coverage and verification quality improve meaningfully under your ownership.
• The coherent interconnect verification effort becomes more scalable, reusable, and predictable because of your contributions.
• Design and architecture teams rely on you as a strong technical partner for difficult protocol, coherency, and integration problems.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in India.

Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.