Staff - Formal Verification Engineer

Responsibilities:

• Identify blocks suitable for applying Formal Verification
• Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics
• Implementation and maintenance of Formal Verification environments in Chisel
• Applying various FV techniques to reduce complexity and prove correctness of DUT
• Debugging RTL to identify causes of failure scenarios
• Guide and train team members on effective usage of Formal Verification tools
• Develop/modify scripts to automate the verification process
• Review formal setups and proofs with design and verification teams
• Maintain and extend assertion libraries

Requirements:

• 8+ years of experience in Formal Verification of Digital Hardware Design
• Extensive experience with Formal Abstraction Techniques and sign-off process
• Familiarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold
• Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ System Verilog
• Knowledge of Object-oriented Programming is a plus
• A keen interest in Processors and Digital systems
• Strong reasoning skills and excellent attention to detail
• Good inter-personal and teamwork skills!
• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in: India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.