Analog Layout Lead

ABOUT LUMILENS

At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.

We’re a well-funded startup backed by Mayfield and led by industry’s veterans who’ve built and scaled some of the most transformative technologies in the industry. This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.

If you're looking for mission, momentum, and the chance to make an outsized impact jump on the rocket ship. We’re just getting started.

POSITION OVERVIEW

We are seeking an Analog Layout Lead to drive full-custom analog and mixed-signal layout for Lumilens’ next-generation silicon platforms. This role will lead complex physical implementation across advanced CMOS nodes, partner closely with circuit design and physical design teams, and establish layout methodologies that ensure performance, reliability, manufacturability, and tape-out readiness across multiple silicon programs.

What You'll Do:

• Lead full-custom layout of complex analog and mixed-signal blocks, including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon platforms.
• Define and enforce analog layout methodologies, design rules, and best practices across the physical design team.
• Drive parasitic-aware layout strategies to meet stringent noise, matching, signal integrity, and power requirements for mixed-signal designs.
• Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus-schematic and parasitic extraction results.
• Own physical verification closure, including DRC, LVS, antenna checks, and sign-off readiness across advanced process nodes.
• Establish floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts.
• Provide technical guidance and layout direction to engineers and contractors, reviewing layouts and driving consistency in methodology, quality, and schedule execution.
• Partner with process technology and design kit teams to evaluate new process nodes, contribute to PDK qualification, and resolve layout-induced performance issues through post-layout simulation analysis.
• Own long-term physical design roadmaps and methodology investments that scale across multiple silicon programs.

Key Qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience.
• 8+ years of experience in full-custom analog and mixed-signal layout for production silicon in advanced CMOS process nodes, preferably 28nm or below.
• 8+ years of hands-on experience with industry-standard layout tools such as Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification.
• Experience leading layout of high-performance analog blocks such as PLLs, voltage regulators, data converters, or high-speed interfaces from concept through tape-out.
• Experience defining and implementing layout methodologies for matching, shielding, noise isolation, and signal integrity in mixed-signal environments.
• Experience collaborating with circuit design teams to interpret simulation requirements and translate them into layout constraints, implementation decisions, and verification closure.
• Experience managing, mentoring, and reviewing the work of layout engineers while coordinating deliverables with external contractors.

Preferred Skills:

• Familiarity with post-layout simulation flows, including RC extraction and back-annotated verification using tools such as Spectre or Calibre.
• Experience contributing to or evaluating process design kits and design rule documentation for new process node bring-up.
• Experience with analog layout for photonics, AI infrastructure, consumer wearable, mobile, or IoT SoCs where power, area, and reliability constraints are critical.
• Experience with 3D stacking technologies, advanced packaging layout considerations, or reusable analog layout templates that improve team-wide efficiency and consistency.