Staff Silicon Physical Design Engineer - Bengaluru

Responsibilities and Duties

• Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs in leading-edge process technologies while meeting ambitious development schedules
• Contributions are expected to span multiple areas and involve:
  • using state-of-the-art EDA tools and in-house Graphcore flows to deliver final designs that are of sign-off quality
  • enhancing existing flows and in-house tools/APIs to support new features and/or methodologies
  • analysis and/or debugging of complex engineering problems leading to workable solutions
  • developing an understanding of emerging technical issues and applying that knowledge to optimise in-house flows and methodologies
• Candidates will be expected to work closely both with other teams within Graphcore and with 3rd party support engineers/contractors, ensuring good communication between all parties, and to contribute meaningfully to the overall efficiency and success of the Physical Team

Essential skills:

• A Degree in Electronic/Electrical Engineering, Computer Science or related subject with 3+ years of Industry experience
• Be highly motivated, a self-starter, and a team player
• Excellent problem-solving skills for debugging issues seen and finding root causes
• Ability to program/script (required to solve design issues, typically in Tcl and Python)
• Experience in 7nm or smaller technologies
• A good breadth of experience with physical design flows including:
  • Floorplanning/Budgeting
  • Synthesis
  • Place and Route
  • Clock CTS
  • Logical Equivalence
  • Timing Analysis
  • Physical Verification (DRC/LVS/ERC)

Desirable skills:

• In depth expertise in one or more aspects of physical design flows
• Structuring of builds to maximise PPA
• Silicon transistor knowledge including std cell libraries and/or memories
• 5D and 3D design (CoWoS, UCIe etc.)
• High speed, high power and/or full reticle chip design
• Ethernet, PCIe, LPDDR, HBM interfaces
• Power integrity and optimization
• 2nm or 3nm technologies
• Chip finishing (pad rings, chip level LVS/DRC/ERC)
• Design for test
• Team management
• Project Planning