Software Engineer

Position Overview:

We are seeking a highly experienced SerDes software engineer to lead the development, bring-up, validation, and optimization of next-generation high-speed interfaces. The successful candidate will work with 224 Gb/s-per-lane Ethernet SerDes, PCI Express, and UCIe chiplet interconnects in advanced networking and compute silicon.

This is a senior technical role requiring strong knowledge of SerDes architecture, PHY initialization, link training, equalization, calibration, diagnostics, and system-level signal-integrity behavior. The engineer will work closely with analog and mixed-signal designers, ASIC architects, firmware teams, validation engineers, board designers, and system software developers.

Key Responsibilities:

• Develop embedded software and firmware for configuring, initializing, calibrating, and monitoring high-speed SerDes PHYs.
• Lead bring-up and optimization of 224G PAM4 SerDes used in Ethernet switch, networking, and accelerator products.
• Develop software support for PCIe SerDes, including link initialization, training, equalization, lane management, error recovery, and diagnostics.
• Develop software support for UCIe die-to-die interfaces, including PHY initialization, link training, lane repair, health monitoring, and failure analysis.
• Implement SerDes adaptation and calibration workflows, including transmitter tuning, receiver CTLE, VGA, DFE, and CDR configuration, adaptive equalization, eye optimization and margining, lane-to-lane skew management, polarity inversion and lane remapping, and background calibration.
• Develop APIs, drivers, firmware interfaces, command-line tools, and diagnostic utilities for SerDes control.
• Support Ethernet auto-negotiation and link training, including Clause 73 and Clause 72/136-related workflows where applicable.
• Support PCIe LTSSM interaction, preset and coefficient negotiation, lane margining, retraining, and recovery.
• Support UCIe link state management, PHY repair mechanisms, sideband interactions, and link reliability features.
• Create automated characterization and production-test software for PRBS generation and checking, BER measurement, eye scans and bathtub curves, jitter and signal-margin analysis, loopback testing, lane failure isolation, and channel and package characterization.
• Analyze difficult link failures across silicon, package, board, connector, cable, and optical-module channels.
• Correlate software-visible SerDes telemetry with oscilloscope, BERT, VNA, and simulation results.
• Develop algorithms and policies for runtime SerDes health monitoring, telemetry, predictive failure detection, and fault recovery.
• Optimize SerDes performance across process, voltage, temperature, channel loss, and manufacturing variation.
• Define software architecture and reusable abstractions that support multiple SerDes IP vendors and PHY generations.
• Create technical specifications, programming guides, bring-up procedures, debug playbooks, and validation plans.
• Mentor engineers and serve as the organization's technical authority for SerDes software and system bring-up.

Required Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Typically 10 or more years of experience in SerDes firmware, PHY software, silicon bring-up, or high-speed interface validation.
• Deep understanding of high-speed serial-link fundamentals, including PAM4 and NRZ signaling, channel loss, jitter, noise, crosstalk, clock and data recovery, transmitter feed-forward equalization, CTLE and decision-feedback equalization, BER and eye diagrams, and forward error correction.
• Hands-on experience bringing up and debugging at least one advanced SerDes generation, preferably 112G or 224G PAM4.
• Strong experience with one or more of: Ethernet SerDes and IEEE 802.3 link training, PCIe Gen5, Gen6, or later-generation PHYs, UCIe or another high-speed die-to-die interface.
• Strong embedded programming skills in C and C++.
• Experience with Python or similar languages for automation, characterization, data analysis, and laboratory equipment control.
• Experience programming SerDes registers through MDIO, I2C, SPI, PCIe configuration space, memory-mapped registers, or vendor-specific interfaces.
• Familiarity with embedded processors, microcontrollers, real-time firmware, interrupts, DMA, and hardware/software interfaces.
• Experience debugging pre-silicon models, emulation platforms, FPGA prototypes, and post-silicon devices.
• Ability to interpret schematics, package and board topology, channel models, IBIS-AMI results, and signal-integrity reports.
• Experience using laboratory equipment such as high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and traffic generators.
• Strong root-cause analysis skills and the ability to debug complex issues spanning analog, digital, firmware, package, board, and system domains.

Preferred Qualifications:

• Experience with 224G-per-lane Ethernet PHYs and 800G, 1.6T, or higher-speed Ethernet systems.
• Experience with PCIe 6.x or PCIe 7.0, including PAM4 signaling, FLIT mode, FEC, and lane margining.
• Experience with UCIe PHY and adapter-layer bring-up in multi-die or chiplet-based systems.
• Familiarity with long-reach, medium-reach, short-reach, very-short-reach, and die-to-die SerDes channels.
• Experience integrating third-party SerDes IP into an ASIC or SoC.
• Experience developing vendor-independent SerDes abstraction layers.
• Knowledge of CMIS, pluggable optics, retimers, active electrical cables, and linear-drive optics.
• Familiarity with IEEE 802.3, PCI-SIG, and UCIe Consortium specifications.
• Experience with SerDes power optimization, fast link recovery, degradation detection, and field diagnostics.
• Experience developing production screening, yield-analysis, and manufacturing-test solutions.
• Experience working with advanced process nodes, 2.5D packaging, interposers, and chiplet-based architectures.
• Track record of technical leadership, cross-functional execution, and mentoring.

Success in This Role:

• Bring up new SerDes interfaces quickly and methodically.
• Establish stable links across challenging channels and operating conditions.
• Convert low-level SerDes capabilities into robust, maintainable software.
• Provide actionable diagnostics rather than opaque link-up or link-down status.
• Reduce silicon bring-up and customer-debug time through automation and strong observability.
• Build a reusable SerDes software architecture spanning Ethernet, PCIe, UCIe, and future high-speed interfaces.

Role Scope:

This position focuses on SerDes control software, embedded firmware, link management, diagnostics, characterization, and system-level optimization. It will work closely with, but does not replace, the analog/mixed-signal SerDes circuit-design function.

Why Join Us?

At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. The pay range for this role is 195,000 - 265,000 USD per year (San Francisco Bay Area).

Notice to Recruiting Agencies:

Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.