Physical Design Engineer

Job Description

We are looking for a motivated and hands-on Physical Design Engineer to join our ASIC team. The ideal candidate should have strong fundamentals in Physical Design and Timing Closure, a passion for solving implementation challenges, and a willingness to learn and grow in a fast-paced startup environment.

Key Responsibilities

Physical Design Implementation

• Participate in block-level and subsystem-level implementation from netlist to GDS.
• Perform floorplanning, placement, CTS, routing, and physical optimization activities.
• Analyze and resolve timing, congestion, utilization, and routing issues.
• Support ECO implementation and timing closure activities.

Timing Analysis & Closure

• Perform setup and hold timing analysis using PrimeTime or equivalent STA tools.
• Debug timing violations and work with design teams to identify and implement solutions.
• Analyze clock quality, timing margins, and constraint issues.

Physical Verification & Signoff

• Support DRC, LVS, ERC, Antenna, and density closure activities.
• Work with Calibre and/or ICV to analyze and resolve physical verification issues.
• Assist in signoff checks and tapeout readiness activities.

Power & PPA Optimization

• Analyze power, performance, and area tradeoffs.
• Support leakage reduction, clock optimization, and power recovery activities.
• Assist in implementing low-power design techniques and optimization strategies.

Automation & Productivity

• Develop and maintain Tcl/Python scripts to improve flow efficiency and automate repetitive tasks.
• Contribute to flow improvements and engineering productivity initiatives.

Collaboration

• Work closely with RTL, DFT, DV, and Physical Design teams to support successful project execution.
• Participate in design reviews and technical discussions.