Principal Physical Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.

Physical Design

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer is required, and a Master's degree is preferred.
• ≥10 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Required Experience:

• Hands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.
• Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.
• Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of System Verilog/Verilog.
• Experience with DFT tools and techniques.
• Experience in working with IP vendors for both RTL and hard-mac blocks.
• Good scripting skills in Python or Perl.

Preferred:

• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.
• Familiarity with DFT test coverage and debug.
• Familiarity with ECO methodologies and tools.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.